1. Field of the Invention
Embodiments of the invention generally relate to the field of semiconductor manufacturing processes and devices, more particular, to methods of depositing silicon-containing films forming semiconductor devices.
2. Description of the Related Art
As smaller transistors are manufactured, ultra shallow source/drain junctions for sub-100 nm CMOS (complementary metal-oxide semiconductor) devices, such as silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices, are becoming more challenging to produce. Such MOS(FET) transistors may include p-channel MOS (PMOS) transistors, and n-channel MOS (NMOS) transistors, depending on the dopant conductivity types, whereas the PMOS has a p-type channel, i.e., holes are responsible for conduction in the channel and the NMOS has an n-type channel, i.e., the electrons are responsible for conduction in the channel.
Silicon based materials may be used in device creation for MOSFET devices. For example, in a PMOS application, the film in a recessed area of the transistor is usually silicon-germanium, and for a NMOS application, the film in the recessed area may be SiC. Silicon-germanium is advantageously used to implant more boron than silicon alone to reduce junction resistivity, which improves device performance, for example, the silicon-germanium interface with the silicide layer at the substrate surface has a lower Schottky barrier than the silicon interface with silicon-germanium.
The recessed areas comprise source/drain extension or source/drain features, which are manufactured by etching silicon to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown silicon-germanium epilayer. The mismatch of lattices between silicon and the silicon-germanium material generates compressive stress which is transferred in the lateral dimension of the junction to create compressive strain in the PMOS channel and to increase mobility of the holes and improve device performance.
Selective silicon-epitaxial (Si-epitaxial) deposition and silicon-germanium-epitaxial deposition permits growth of epilayers on silicon (Si) moats with no growth on dielectric areas. Selective epitaxy can be used in semiconductor devices, such as within source/drains, source/drain extensions, contact plugs, and base layer deposition of bipolar devices. Additionally, selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process may be omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. Improved junction depth also produces compressive stress. One example of the use of silicon containing materials in device creation is for MOSFET devices.
However, in ultra shallow source/drain junction applications for use in decreasing feature sizes, conventional manufacturing processes result in increased series resistance and reduced compressive stress in PMOS devices. Also, silicidation of the surface of the source/drain regions of a transistor results in junction consumption that increases the series resistance even further and produces tensile stress which counteracts the desired compressive stress formed in the transistor. As such, conventional etching and deposition processes for MOSFET under the silicon-germanium incorporation have been less than desirable and have resulted in undesirable dopant diffusion and undesirable stress relaxation effects.
Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon compounds that have an enriched dopant concentration and incorporation into semiconductor devices with improved device performance.